Circuit synthesis is a software-implemented tool for designing circuits based on providing inputs corresponding to circuit components, desired behavior, and constraints in an interactive or batch manner. Circuit synthesis can typically be implemented for complementary metal-oxide semiconductor (CMOS) circuit design, based on behavioral Register Transfer Level (RTL) code which is typically written in VHSIC Hardware Description Language (VHDL), Verilog, or System C. As applications for superconducting circuit systems become more prevalent, using circuit synthesis can be a manner to more quickly and efficiently optimize a superconducting circuit design, including Reciprocal Quantum Logic (RQL) circuits. In CMOS circuits, the component building blocks are classified as combinatorial (i.e., the output depends only on current inputs), such as an AND gate, or sequential (i.e., the output depends on current and previous inputs), such as a flip-flop (also known as a FF or register) or a level-sensitive latch. Sequential devices have the property of memory or storing a state. In RQL, these strict combinatorial and sequential classifications do not apply because a Josephson transmission line (JTL) is technically sequential, but it is frequently used more like a buffer where it is combinatorial. The FF is edge-sensitive to the clock and is the corner stone of a synchronous design methodology supported by synthesis.
Some circuit devices that are typically required in a CMOS synthesis system, such as an edge-triggered flip-flop device, cannot be efficiently built in RQL. Most current commercial CMOS synthesizers require the component library to contain a sequential FF element. The role of the synthesizer is to take behavioral RTL code and translate it into a netlist comprised of cells in the component library for some fabrication process. Additional separate tools, while not part of the synthesis process, can be used in the overall flow. A separate tool know as a simulator can typically be used to verify functional correctness of the RTL code before it is synthesized. After synthesis, other tools can be used to implement the steps of placement and routing. During place and route, netlist changes may be introduced either automatically by tools or with manual edits, for any of a variety of purposes (e.g., satisfying timing requirements using a static timing analysis tool). The simulator can be run again on the final gate-level netlist produced after place-and-route or logical equivalency checking between gate-level netlist and RTL code as a final verification step. Other physical verification steps like layout-versus-schematic (LVS), a design rule check (DRC), electrical rule check (ERC), and design for manufacturing (DFM) checks can also be used before a design is actually fabricated.